The present invention relates to a communication system, and more particularly to an echo canceller suitable for a subscriber line digital transmitter in an ISDN (integrated services digital network).
A subscriber digital transmitter usually comprises two units, a line termination (LT) at a switching station and a network termination (NT) at a terminal a signal (down-going signal transmitted from LT to NT and a signal (up-going signal) transmitted from NT to LT are separated by balancing circuits provided in the terminations of LT and NT. As to the down-going signal from LT to NT, a waveform is deformed at an input point of NT because of high-frequency attenuation characteristic of the line. Accordingly, an inter symbol interference (ISI) occurs so that waveforms of adjacent ones of sequentially transmitted signals overlap.
Further, because of impedance mismatching between the line and the balancing circuit, the up-going signal and the down-going signal are not perfectly separated and an echo signal component appears so that a portion of the up-going signal is combined with the down-going signal. Accordingly, NT comprises a circuit for eliminating the intersymbol interference component and an echo canceller which generates a quasi-echo signal for cancelling the echo signal.
In NT, a received clock is generated by a PLL (phase locked loop) in order to synchronize with a timing of the transmitted data. The phase shifting of received clock is effected by momentarily switching a frequency division ratio of a master clock. For example, three different frequency division ratios 1/(A-1), 1/A and 1/(A+1) (where A is a positive integer) are prepared. Normally, synchronization is effected at 1/A. Because of a problem due to precision of the master clock, the phase of the received clock in NT always fluctuates to the transmission timing of LT. If the synchronization between LT and NT deviates beyond a predetermined range, the frequency division ratio is switched to 1/(A+1) or 1/(A-1) for one clock generation period to correct the deviated phase so that the clock is synchronized with the transmission timing of LT. From the second clock, the transmission clock is generated at the original frequency division ratio 1/A. When the phase of the received clock is momentarily shifted for synchronization, the phase of the transmitted clock used when data is transmitted from NT is also shifted. The echo canceller of NT samples the received signal from LT on which the echo has been overlapped by the signal transmitted by NT, at rising edges of the received clock and generates quasi-echo signal of the opposite polarity for cancelling the echo, based on the transmitted signal.
In the following description, the phase shifting means to momentarily switch the frequency division ratio to a different ratio for only one clock generation period for synchronization, and the phase shift means phase shifted status. As the phase of the received clock shifts, a sampling position of the received signal shifts. Thus, a tap coefficient (rewritable constant) for generating a cancel signal which the echo canceller has had before the phase shift is no longer proper and it should be corrected to a value which permits perfect cancellation of the echo in accordance with the phase shift.
The echo canceller usually has several tens of (for example, 50) taps (sampling points for the echo signal) so that it can cancel as many echos due to the transmitted signal as the number of taps. If the transmission/reception clock is always constant, the echo can be cancelled by one tap coefficient, but if the clock of different period is used for only one clock generation period, the sampling point is shifted and hence the tap coefficient should be corrected.
An echo canceller in full duplex transmission in a subscriber line digital transmitter is disclosed in JP-A-61-256833 filed on Jan. 29, 1986 by British Telecommunications Public Limited Co. It uses an adaptive filter having a tap coefficient correction function for phase shift of sampling timing of an echo signal to be cancelled. The adaptive filter comprises a plurality of cascade-connected delay circuits to which voltage levels of the transmitted signals are applied. An output stage of each delay circuit has a multiplier for multiplying a predetermined value called a tap coefficient to a delay circuit output a.sub.i, and a memory for storing the tap coefficient .alpha..sub.i .multidot.A sum ##EQU1## of products a.sub.i .multidot..alpha..sub.i of the delay circuit output a.sub.i and the tap coefficient .alpha..sub.i is calculated as an echo cancelling signal to cancel the echo signal, where S is the number of taps. In case a phase shift of a received clock occurs, an adaptive feedback loop for correcting the tap coefficients to optimum values based on a difference (residual echo signal) between the quasi-echo signal and the actual echo signal is also provided.
In the correction of the tap coefficient disclosed in the JP-A-61-256833, a product of the residual echo signal, the phase shift direction and the amount of phase shift are integrated to determine a primary term of a Taylor approximation of the echo signal, the phase shift direction and the amount of phase shift are multiplied to the primary term of the Taylor approximation to determined a tap coefficient correction y.sub.i, and it is added to the tap coefficient of the adoptive filter to determine a new tap coefficient .alpha..sub.i '=.alpha..sub.i +y.sub.i. As a result, a new quasi-echo signal ##EQU2## is produced. Each time the phase of the received clock is shifted, the new tap coefficient is determined by calculation. In this system, because of large amount of processing, a large capacity memory is required. Further, since the calculation of the primary term of the Taylor approximation includes noise components such as residual echo signal because of limited tap numbers of the echo canceller near end crosstalk from adjacent lines, a correct y.sub.i cannot be produced and a convergence time of the echo canceller increases.